1. Field of the Invention
The present invention relates to multichip integrated circuit module assemblies and more particularly relates to an improved arrangement for coupling fine pitch pads of integrated circuit chips to coarse pitch pads of an interconnection substrate.
2. Description of the Prior Art
Many types of electronic devices employ a number of integrated circuit chips which are interconnected to one another and assembled in a single package or module. These multichip modules may employ state of the art semiconductor devices that are typically 0.5.times.0.5 inches in size with peripherally positioned input output contacts having a 0.004 inch pitch (e.g. center to center spacing). This pitch requires use of connecting lines and spaces between lines of 0.002 inches. Most commonly these multichip modules are mounted on multilayer polyimide dielectric substrates that employ thin film processes for forming electrically conductive traces to interconnect with the various chip contacts. The multilayer dielectric substrates are made employing techniques that have been initially developed for various types of semiconductor processing. They can be made with fine pitch traces but are time consuming and expensive to fabricate.
A different, less costly technology, termed Low Temperature Co-fired Ceramic (LTCC), has been developed for forming multilayer interconnecting circuits for multilayer electronic packages. LTCC technology employs multiple layers of ceramic tape processed by thick film techniques to provide conductive circuit traces and interconnections extending between the many layers of the LTCC module. The LTCC module is capable of high volume low cost manufacturing but is subject to the limitation of relatively coarse pitch interconnecting traces and vias. In the LTCC process, metalization is applied using thick film technology which limits the pitch of conductors and connecting elements to approximately 0.016 inches. Attempts to provide LTCC modules with a much finer pitch greatly degrades the manufacturing yield. In general, the requirement of a coarse pitch is not a major handicap for LTCC processing since a large number of layers of this multilayer substrate can be employed. However, fine pitch lines or connections cannot be formed in the LTCC module, and thus, an integrated circuit chip having a set of fine pitch peripheral contacts cannot be mounted on or otherwise accommodated on the top layer of the multilayer LTCC module. Arrangements for directly connecting the peripheral contact pads of the integrated circuit chip to the more widely spaced pads of the LTCC module require excessive amounts of area of the module and thus prevent spacing of several integrated circuit chips close to one another on the surface of the module.
Attempts have been made in the past to form thin film type interconnect circuits directly on the surface of the LTCC module to which the integrated circuit chips are mounted. The application of semiconductor processing techniques directly to the LTCC module requires difficult, time consuming and expensive procedures. Generally, testing of such circuits can be achieved only after the entire package has been assembled, resulting in greater costs and more failures because inadequacies of subassemblies cannot be detected at an earlier stage.
The combination of thin film technology with a ceramic substrate for packaging applications might be perceived as a simple extension of semiconductor technology to cruder dimensions. In practice, there are critical challenges in combining glass ceramic (LTCC) and thin film technology. These include the matching of a photolithographic pattern to a distorted sintered ceramic pattern, the surface roughness and non-homogeneity of the ceramic surface, the requirement for defect free wiring over the entire area of the substrate, the relatively high current carried which requires much thicker conductors, and finally, multiple metallurgies are required for various interconnection functions.
Accordingly it is an object of the present invention to provide a multichip module in which above-mentioned problems are avoided or minimized.